The invention relates to a method of dividing the frequency of an electronic signal, the method comprising the steps of:
preloading a first predetermined value in an up/down counter,
clocking the up/down counter by means of said electronic signal,
detecting a state in which the up/down counter has a second predetermined value, and
again preloading the first predetermined value in the up/down counter.
Such methods are currently used in multiple applications, for example, in phase-locked loops intended to regulate the frequency of an oscillator. These phase-locked loops usually comprise:
a first local oscillator intended to supply an output signal having an oscillation frequency determined by the value of a tuning voltage,
a second local oscillator intended to supply, via a frequency divider having a programmable division ratio, a reference signal having a reference frequency.
a phase/frequency detector intended to compare the oscillation frequency with the reference frequency and to supply control signals representing the result of said comparison, and
a charge pump whose conduction is intended to be controlled by the control signals, an output of the charge pump being connected to a capacitance intended to generate the tuning voltage at its terminals.
In such a phase-locked loop, the method described in the opening paragraph is performed within the frequency divider whose division ratio is determined by the difference between the first and second predetermined values. In principle, the frequency divider includes N flip-flops arranged in cascade, each of which can be preloaded by a bit of a selection signal defining one of the predetermined values.
In the known frequency division methods, the preloading operations are performed synchronously, i.e. all flip-flops are simultaneously preloaded as soon as the frequency divider has received an authorization for preloading. As each flip-flop receives its energy from a positive and a negative power supply terminal, the change of state of a flip-flop requires a current to be drawn from the positive power supply terminal. The frequency divider is mostly realized in an integrated form within an integrated circuit having power supply pins to which the power supply terminals are connected by means of conducting wires that have an inductive character. The applicant has found that the preloading operations cause perturbations in the operation of the frequency divider and in that of other elements with which the frequency divider shares its energy supply. Indeed, the applicant has noticed that a simultaneous change of states of a large number of flip-flops, which occurs periodically, involves periodical variations of the power supply terminal potentials because of the inductive character of the conducting wires connecting the power supply pins to the power supply terminals, which variations generate noise in all of the electronic signals that are present in the elements fed by means of said power supply terminals.
It is an object of the invention to remedy this drawback to a great extent by proposing a method of dividing the frequency of an electronic signal, in which method periodical preloading operations are performed without significantly perturbing the potentials of the power supply terminals.
A method as described in the opening paragraph is characterized in that the preloading operations are performed asynchronously.
In accordance with this method, there are no longer situations in which a large number of flip-flops simultaneously change their state, which prevents the periodical, strong current appeals as described above from occurring and perturbing the potentials of the power supply terminals.
In a particular embodiment of the invention, the up/down counter is constituted by N flip-flops arranged in cascade, each being intended to be preloaded periodically, while a flip-flop of the rank i (for i=2 to N) is only preloaded on the condition that the flip-flop of the rank (ixe2x88x921) has been preloaded previously.
In this embodiment, the flip-flops are preloaded one after the other. The consumption of current required for a preloading operation is thus spread with respect to time, which considerably limits the amplitude of the potential variation of the power supply terminals due to this current consumption.
As stated hereinbefore, the invention in one of its embodiments also relates to a frequency divider comprising N flip-flops each having a clock input, an input for enabling the preloading operation, and an output, the output of a flip-flop of the rank i (for i=1 to Nxe2x88x921) being connected to the clock input of the flip-flop of rank (i+1), the clock input of the flip-flop of rank 1 being intended to receive an input signal of the divider, the output of the flip-flop of the rank N being intended to supply an output signal of the divider, frequency divider characterized in that it is provided with inhibition means prohibiting simultaneous preloading of all flip-flops.
The inhibition means advantageously comprise delay means arranged in such a way that a flip-flop of the rank i (for i=2 to N) can only receive authorization for a preloading operation on the condition that the flip-flop of rank (ixe2x88x921) has been preloaded previously.
In a preferred embodiment of the invention, the inputs for enabling the preloading operation of two flip-flops of consecutive ranks are interconnected via a delay cell.
This structure ensures in a simple and low-cost manner that the flip-flops are preloaded one after the other, rather than simultaneously, as is the case in the known frequency dividers.
If the invention can be used in all types of applications using frequency division, its use is particularly advantageous in an apparatus for receiving radioelectric signals, such as a radiotelephone or a television, comprising an input stage allowing reception of a signal whose frequency is selected from within a given range of frequencies and its transformation into an electronic signal referred to as radio signal, in which apparatus a conversion of the frequency, based on the selected frequency, to a predetermined intermediate frequency is realized by means of a mixer intended to receive the radio signal and the output signal of a first local oscillator, apparatus characterized in that the frequency of the output signal of the first local oscillator is regulated by means of a phase-locked loop including a frequency divider as described hereinbefore.